NB4N111KMNG產(chǎn)品概述
The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply. Clock input pins incorporate an internal 50 Ω on die termination resistors. Outputs can interface with LVDS with proper termination. The NB4N111K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N111K's performance to distribute low skew clocks across the backplane or the motherboard.
Features:
Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and 400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
<1 ps RMS Additive Clock jitter
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Differential HCSL Output Level or LVDS with Proper Termination
These are Pb-Free Devices
Datasheet
